1. Field of Invention
The present invention relates to a type of electrically erasable programmable read only memory (EEPROM). More particularly, the present invention relates to a flash EEPROM that utilizes hot carrier injection to conduct programming operations and negative gate voltage to conduct channel erase operations.
2. Description of Related Art
Conventional flash EEPROM that carries out memory erase operations with a high voltage applied to the source terminal has a number of drawbacks. For example, the flash EEPROM originally designed by Intel has the following drawbacks. First, the high voltage at the source junction during memory erase operation will establish band-to-band tunneling conduction, which will lead to the generation of a rather high memory erase current flowing from the source terminal to the substrate. The generation of such a high current through an on-chip charge pumping circuit is very difficult, therefore an extra high voltage source of about 12V needs to be supplied from outside. Secondly, besides establishing band-to-band tunneling conduction at the source terminal junction, a high voltage at the source terminal junction also generates hot holes. These hot holes can easily be trapped inside an oxide layer causing the so-called "gate disturbance", thereby lowering the charge retention capability of a memory cell. Thirdly, to provide a high voltage at the source junction, a double diffused graded junction structure is required. The double diffused graded junction structure occupies substantial substrate area making the reduction of dimensions for the next generation of memory device rather difficult.
Another type of conventional flash EEPROM can be found in the design suggested by AND in U.S. Pat. No. 5,077,691. In the design, a higher negative gate voltage and a relatively low positive voltage are applied to the source terminal junction of a memory cell. Although this design can resolve most of the problems related to the conventional Intel flash memory, the mechanism of memory erase is still carried out at the source terminal (known as source-terminal erase). A device that employs the source-terminal erase mechanism generally has a non-uniform erasing property, and hence the reliability for these types of devices is normally rather low.
In light of the foregoing, there is a need to provide an improved flash EEPROM structure.